Very large scale integration (VLSI) is the process of making an integrated circuit (IC) by combining thousands of transistors into one chip [1]. The paper entitled “Delay-power efficient VLSI architecture design for robust proportionate adaptive filter” written by Lakshmaiah et al. in this paper discusses a robust proportional adaptive filtering algorithm and an efficient VLSI architecture for spare system identification in impulsive noise, several types of algorithms are combined to get optimal results. This paper has been published in The Indonesian Journal of Electrical Engineering and Computer Science (IJEECS), volume 26, issue 1, 2022.
In the paper, Lakshmaiah et al. have collected reliable algorithms and made a comparative analysis of all the collected algorithms in terms of convergence, hardware and performance. The authors concluded that the delayed μ-law least mean logarithmic square (DMPLMLS) algorithm is a better VLSI solution under impulsive noise conditions for spare system identification. The filters of order 32 and 64-bit are used and the results obtained are data arrival time (DAT) which shows the time of the peak point in the circuit, adaption delay (AD) is used to indicate the number of cycles, area-delay product (ADP) shows the product of area and DAT, total delay in the circuit is indicated by (D), energy per sample (EPS) shows the product of power and DAT of the circuit which is listed in Table 1.
Table 1. Synthesized results of derived algorithms using 90 nm CMOS process
By: D. Ilham
Algorithm and architecture design of adaptive filters with error nonlinearities| Mula | IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance analysis of proportionate-Type LMS algorithms| Gogineni | Signal Processing – Algorithms, Architectures, Arrangements, and Applications Conference Proceedings, SPA
Robust proportionate adaptive filter architectures under impulsive noise| Mula | IEEE Transactions on Very Large Scale Integration (VLSI) Systems